The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device which has a memory cell in which electrically erasable programmable non-volatile memory cells and volatile random access memory cells are provided with a one-to-one relationship.
In the semiconductor memory device of the type described above, write and read operations are successively carried out with respect to the volatile memory cells during operation of the semiconductor memory device. On the other hand, when stopping the operation of the semiconductor memory device, data stored in the volatile memory cells are transferred and stored into the non-volatile memory cells. When resuming the operation of the semiconductor memory device, the data stored in the non-volatile memory cells are recalled and transferred to the volatile memory cells so that the operation can be resumed from the state before the operation was stopped. By providing one non-volatile memory cell with respect to each volatile memory cell, the storing into the non-volatile memory cell and the recalling to the volatile memory cell can respectively be made simultaneously for each of the memory cells. In other words, the storing and the recalling are respectively made with respect to all of the memory cells in one operation, and not one memory cell at a time. Hence, the time required to make the storing and the recalling within a short time.
FIG.1 generally shows an example of a conventional semiconductor memory device of the type described above. A memory cell array 10 includes a plurality of memory cell parts, and each memory cell part is provided at an intersection part of a word line WL and a bit line pair BL and BL. Each memory cell part is made up of a volatile random access memory cell MC.sub.S and an electrically erasable programmable non-volatile memory cell MC.sub.E. The memory cell MC.sub.S corresponds to a memory cell of a static random access memory (SRAM), and the memory cell MC.sub.E corresponds to a memory cell of an electrically erasable programmable read only memory (EEPROM). A relatively high voltage V.sub.HH on the order of 20 V is required to write data into the memory cell MC.sub.E. Hence, a booster circuit 12 is provided to generate this relatively high voltage V.sub.HH. A timer circuit 14, a store end judging circuit 16 and a mode selection circuit 18 are additionally provided and connected as shown.
A chip select signal CS, a write enable signal WE, a store signal ST and an array recall signal AR are supplied to the mode selection circuit 18. The mode selection circuit 18 supplies the store signal ST to the booster circuit 12, the timer circuit 14 and the end judging circuit 16, and supplies the recall signal AR to a recall control circuit 20. The recall control circuit 20 supplies a recall control signal ARC to the memory cell MC.sub.E, and also supplies a control signal to a power source switch VccSW in a recall mode.
A memory access address is made up of a plurality of bits. Predetermined bits Ai of the memory access address are supplied to an address buffer 24, while remaining bits Aj of the memory access address are supplied to an address buffer 26. The predetermined bits Ai are supplied from the address buffer 24 to an X-decoder 28 which selects a word line. On the other hand, the remaining bits Aj are supplied from the address buffer 26 to a Y-decoder 30 which selects a gate of a Y-gate (or column gate) 32. Data read out from the memory cell array 10 is selected at the Y-gate 32 and is amplified in a sense amplifier 34. An output of the sense amplifier 34 is supplied to a buffer 36 which outputs a read data DO. On the other hand, a write data DI is supplied to the memory cell array 10 via a buffer 38 and the Y-gate 32, and is written into the memory cell parts selected by the word line, similarly as in the case of a normal memory device.
FIG. 2 shows an example of the memory cell part which is made up of the memory cells MC.sub.S and MC.sub.E. The memory cell MC.sub.S is a flip-flop, similarly as in the case of a memory cell of the normal SRAM. In this case, the memory cell MC.sub.S includes depletion type MOS transistors TD.sub.1 and TD.sub.2 which are used as loads and enhancement type MOS transistors TE.sub.1 and TE.sub.2 which are used as drivers. Transistors TE.sub.3 and TE.sub.4 are used as transfer gates and couple the memory cell MC.sub.S to the bit line pair BL and BL.
On the other hand, the memory cell MC.sub.E is shown in FIG. 2 as an equivalent circuit which includes capacitors CT.sub.1 through CT.sub.3 and CT.sub.N. A node N.sub.5 which corresponds to a floating gate FG is connected to a gate of a transistor T.sub.M. Lines 1.sub.1 and 1.sub.2 for coupling the memory cell MC.sub.E to the memory cell MC.sub.S are respectively connected to nodes N.sub.1 and N.sub.2 of the memory cell MC.sub.S. The transistor T.sub.M is connected to the line 1.sub.2 together with a transistor T.sub.A which receives the recall control signal ARC. The lines 1.sub.1 and 1.sub.2 are respectively connected to gates of transistors T.sub.1 and T.sub.2. The line 1.sub.1 is grounded via a capacitor CT.sub.O, while the line 1.sub.2 is grounded via the transistors T.sub.A and T.sub.M.
The write and read operation with respect to the memory cell MC.sub.S is carried out similarly as in the case of the normal SRAM.
In a store mode in which the data stored in the memory cell MC.sub.S is stored into the memory cell MC.sub.E, the mode selection circuit 18 outputs the store signal ST. For example, it is assumed for the sake of convenience that the data "0" is stored in the memory cell MC.sub.S, and that the signal levels at the nodes N.sub.1 and N.sub.2 respectively are high (5 V) and low (0 V). In this case, the transistor T.sub.1 is ON, the transistor T.sub.2 is OFF, and the potential at a node N.sub.3 of the memory cell MC.sub.E is the ground potential. Because the booster circuit 12 generates the relatively high voltage V.sub.HH in response to the store signal ST, the capacitor CT.sub.1 of the memory cell MC.sub.E is charged to the voltage V.sub.HH, and the three capacitors CT.sub.3, CT.sub.N and CT.sub.2 receive the voltage V.sub.HH in the series-connected state. In this case, the booster circuit 12 generates a voltage V.sub.HH of 20 V in response to four clocks. The capacitor CT.sub.N has a tunneling layer, and the floating gate FG (node N.sub.5) has a positive potential since there is input and output of charge through the tunneling layer. Hence, data "0" is stored in the memory cell MC.sub.E in this state, and the transistor T.sub.M is ON.
On the other hand, when the data "1" is stored in the memory cell MC.sub.S and the potentials at the nodes N.sub.1 and N.sub.2 respectively are low and high, the transistor T.sub.1 is OFF and the transistor T.sub.2 is ON. Thus, a node N.sub.4 of the memory cell MC.sub.E has the ground potential. In this case, the capacitor CT.sub.3 is charged to the volta V.sub.HH, and the three capacitors CT.sub.1, CT.sub.2 and CT.sub.N receive the voltage V.sub.HH in the series-connected state. The floating gate FG (node N.sub.5) has a negative potential. Accordingly, data "1" is stored in the memory cell MC.sub.E in this state, and the transistor T.sub.M is OFF.
In a recall mode in which the data stored in the memory cell MC.sub.E is recalled and stored into the memory cell MC.sub.S, the mode selection circuit 18 outputs the recall signal AR. The recall control circuit 20 outputs a high-level recall control signal ARC in response to the recall signal AR. The transistor T.sub.A turns ON in response to the high-level recall control signal ARC. Since the transistor T.sub.M is ON if the data "0" is stored in the memory cell MC.sub.E, the potential at the node N.sub.2 of the memory cell MC.sub.S is lowered to the ground potential via the transistors T.sub.A and T.sub.M, and the node N.sub.1 is grounded via the capacitor CT.sub.O. Consequently, the potentials at the nodes N.sub.1 and N.sub.2 respectively become high and low as a power source voltage Vcc of the memory cell MC.sub.S is raised, and the transistor TE.sub.2 turns ON and the transistor TE.sub.1 turns OFF. As a result, the memory cell MC.sub.S is returned to the original state in which the data "0" is stored in the memory cell MC.sub.S.
The transistor T.sub.M is OFF if the data "1" is stored in the memory cell MC.sub.E, the potential at the node N.sub.2 of the memory cell MC.sub.S is raised as the power source voltage Vcc is raised, and the potential rise at the node N.sub.1 is delayed by the provision of the capacitor CT.sub.O. Accordingly, the potentials at the nodes N.sub.2 and N.sub.1 respectively become high and low, and the transistor TE.sub.1 turns ON and the transistor TE.sub.2 turns OFF. As a result, the memory cell MC.sub.S is returned to the original state in which the data "1" is stored in the memory cell MC.sub.S.
When the mode selection circuit 18 outputs the store signal ST in response to the external store signal ST or outputs the recall signal AR in response to the external recall signal AR, the store or recall operation is made for all of the memory cells of the memory cell array 10. For this reason, the storing of the data into the memory cells MC.sub.E and the recalling of the data into the memory cells MC.sub.S can be made within a short time.
The semiconductor memory device of the type described above does not have an extremely large memory capacity. For example, the memory capacity is 256.times.4 bits. In addition, the store end judging circuit 16 shown in FIG. 1 monitors the generation of a pulse which is used to generate the voltage V.sub.HH, and the end of the store operation is detected when four such pulses are generated.
The semiconductor memory device of the type described above is sometimes referred to as a non-volatile RAM (NVRAM). And in such NVRAMs, a noise which is generated when the power source is turned ON/OFF, a skew of the signal when the mode of the NVRAM is switched and the like may cause an erroneous store operation.
In EPROMs, the operator does not need to make a special operation such as applying a high voltage to terminal pins of the EPROM when carrying out a write operation, and for this reason, an erroneous write operation is unlikely to occur. On the other hand, in NVRAMs, once the store signal ST is supplied to the mode selection circuit 18, operations such as raising the internal voltage are carried out automatically and the store operation is carried out to store the data into the memory cells MC.sub.E. The pulse width of the store signal ST is on the order of nano-seconds (ns), and a noise may be mistaken as the store signal ST. When the noise is mistaken as the store signal ST, the store operation is carried out automatically in error. A similar situation occurs when a noise is mistaken as the recall signal AR and the recall operation is automatically carried out in error. However, problems occur if the operator is not aware of such erroneous store and recall operations which are carried out naturally in error.
As measures against the erroneous store and recall operations, two methods are conceivable.
According to a first method, a power source monitoring circuit is provided within the chip of the NVRAM. The power source voltage is normally 5 V, and the circuits of the NVRAM will not operate correctly if the power source voltage becomes 3 V or less. An erroneous output signal may be generated when the circuits of the NVRAM do not operate correctly, and this erroneous output signal may be mistaken as the store or recall signal ST/e,ovs/AR/ . Hence, the first method monitors the power source voltage by the power source monitoring circuit and prohibits the store or recall operation when the power source voltage becomes 3 V or less.
On the other hand, a reject circuit is provided to prevent the NVRAM from operating in response to signals having narrow pulse widths. Generally, the noise has a narrow pulse width. Hence, the second method rejects signals which have pulse width less than a predetermined pulse width by the reject circuit and recognizes the signal as the store or recall signal ST/AR only when the pulse width of the signal is greater than or equal to the predetermined pulse width.
However, the first and second methods described above cannot prevent all erroneous store and recall operations.
When the erroneous store operation does occur, this causes data error in the NVRAM because the erroneous store operation is carried out simultaneously with respect to all bits. But data error also occurs when defective memory cells exist in the NVRAM. Accordingly, it is impossible to distinguish the data error caused by the erroneous store operation from the data error caused by the defective memory cells.
But when a data processing system fails and it is detected that the failure originates from the memory device, for example, the method used to remove the failure is different depending on whether the data error is caused by the erroneous store operation or by the defective memory cells. In the case of the EPROM, the write operation is carried out by applying a relatively high voltage to the EPROM, and it is always possible to know that the data was intentionally written by the operator since the write operation would not be carried out unless the relatively high voltage is applied. However, in the case of the NVRAM, it is unclear whether the data was intentionally stored or stored naturally in error.
Therefore, there is a demand to realize an NVRAM in which it is possible to determine whether the data was stored intentionally or written naturally in error.